The present invention relates to a method of fabricating a semiconductor device having at different depths a plurality of regions to be contacted.
In recent years, reduction in DOF (Depth of Focus) margin in a lithography step has become increasingly important with the trend of the reduced design rule, and to extend such a DOF margin in a lithography step, an underlying layer has been required to be subjected to global planarization. However, when different polysilicon (polycrystalline silicon) interconnection layers are respectively provided in a cell region and a peripheral region, for example, in the case of a DRAM (Dynamic Random Access Memory), the depths of contact holes formed in both the regions are made different from each other by global planarization. For example, an aspect ratio (depth/diameter) of a substrate contact hole formed in a peripheral region might be 4 or more under a design rule of 0.25 .mu.m. In this case, there is a possibility that the depth of the contact hole formed in the peripheral region is different from that of a contact hole formed in a cell region by about 1 .mu.m. For this reason, it has become still more difficult to form a conductive plug layer in the contact holes formed in both the regions in the same processing step. Hereinafter, a related art method of fabricating a semiconductor device will be basically described with reference to FIGS. 2A to 2E.
As shown in FIG. 2A, an insulting layer 12 made from silicon oxide or the like, which has a stepped surface, is formed on a P-type or N-type semiconducting substrate 11, and a polysilicon layer 13 as an interconnection layer is formed in an intermediate portion of a higher region of the insulating film 12. Here, as shown in FIG. 2B, an interlayer insulating film 14 made from silicon oxide or the like is formed over the entire surface of the insulating film 12 to a thickness of about 300 nm, and as shown in FIG. 2C, the entire surface is polished by a chemical-mechanical polishing (CMP) process or the like to be planarized. After that, as shown in FIG. 2D, a photoresist 15 having a contact hole forming pattern is formed over the entire surface by lithography, followed by anisotropic etching using the photoresist 15 as a mask, to simultaneously form both a contact hole 16 reaching the polysilicon layer 13 and a contact hole 17 reaching the original semiconducting substrate 11 in the lower region. At this time, as shown in FIG. 2D, since the depth from the surface to the polysilicon layer 13 is different from the depth from the surface to the semiconducting substrate 11, when the etching is effected such that the deep contact hole 17 reaches its underlying layer (semiconducting substrate 1), the underlying layer (polysilicon layer 13) of the shallow contact hole 16 is cut by the etching.
Next, as shown in FIG. 2E, the photoresist 15 is removed, and a barrier metal layer 18 is formed by sputtering and a tungsten layer 19 is formed by a BLK-W-CVD (blanket-tungsten-chemical vapor deposition) process in the contact holes 16, 17. More specifically, the barrier layer 18 for improving adhesion strength and the conductive tungsten layer 19 are formed, followed by etching-back over the entire surface, to remove the barrier metal layer 18 and the tungsten layer 19 excluding the interiors of the two contact holes 16, 17. At this time, since an aspect ratio of the contact hole 17 is excessively larger, a void 20 is formed in the tungsten layer 19.
In this way, according to the related art method, when deep and shallow contact holes 17, 16 are simultaneously formed, the underlying layer (polysilicon layer 13) of the shallow contact hole 16 is cut and in the worst cases, it may be pierced. To cope with such an inconvenience, the thickness of the underlying layer (polysilicon layer 13) of the shallow contact hole 16 must be made sufficiently thick, which causes another inconvenience that the height of the stepped portion of the insulating layer 12 is further increased.
The related art presents another disadvantage that it is difficult to form an interconnection at a high reliability because the barrier metal layer 18 is not contact hole 17 and also the void 20 is formed in the tungsten layer 19.